The invention generally relates to a clocking architecture.
A typical computer system may include a bridge to transfer data between busses of the computer system. For example, the bridge may include a memory interface to control the storage and retrieval of data from a system memory. To accomplish this, the memory interface typically initiates read and write operations over a memory bus that is coupled between the memory interface and the system memory.
For example, for a write operation, the memory interface may furnish data signals to data lines (of the memory bus) that indicate data for the write operation. Typically, the memory interface ensures that the data signals are synchronized to a system clock signal that is used to synchronize transactions that occur over the memory bus.
The memory interface typically includes signal buffers (one for each data line) to drive the data lines of the bus with the data signals during a write operation. Each buffer may introduce a significant delay to its data signal and thus, cause the data signal to lose synchronization with the clock signal. One solution is to couple delay lines in series with the clock and data lines to achieve synchronization. However, the lengths of the data lines may vary, and the circuitry that is connected to the data lines may introduce different loads on the data lines, thereby placing different loads on the signal buffers and causing the signal buffers to introduce different delays. Thus, it may be very difficult to synchronize the data and clock signals using this technique.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.